Search - code vhdl pwm

[VHDL-FPGA-Verilog] vcpwmcpldcar

Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Platform: | Size: 959488 | Author: hxf | Hits:

[VHDL-FPGA-Verilog] Source

Description: PWM的Verilog HDL代码用于FPGA-PWM of the Verilog HDL code for FPGA
Platform: | Size: 2048 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] PWM_CT

Description: PWM调制输出、定时和计数控制器的芯片设计-PWM modulation output, timing and count controller chip design
Platform: | Size: 5120 | Author: 李利歌 | Hits:

[VHDL-FPGA-Verilog] PWM

Description:
Platform: | Size: 433152 | Author: 黄朝谦 | Hits:

[VHDL-FPGA-Verilog] SVPWM

Description: 这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序-This is a motor SVPWM Speed VHDL source code control procedures, including the main program and test rtl simulation program sim
Platform: | Size: 13312 | Author: 杨国超 | Hits:

[VHDL-FPGA-Verilog] FPGA_PWM

Description: 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple modification to the application!
Platform: | Size: 1024 | Author: 温海龙 | Hits:

[SCM] Source

Description: PWM Verilog源代码，可以通过仿真测试-PWM Verilog source code, can be tested through simulation
Platform: | Size: 2048 | Author: shuichengwen | Hits:

[SCM] pwm

Description: pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Platform: | Size: 1024 | Author: chenhaoran | Hits:

[VHDL-FPGA-Verilog] pmw2ppm

Description: Vhdl code PPM to pwm converte
Platform: | Size: 4096 | Author: SANTOSH | Hits:

[VHDL-FPGA-Verilog] pwm_gen

Description: PWM _Generator VHDL code
Platform: | Size: 1024 | Author: kiran | Hits:

[VHDL-FPGA-Verilog] fpga-pwm

Description: 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Platform: | Size: 1163264 | Author: 黄家武 | Hits:

[Driver Develop] FPGA_SOPC_PWM

Description: 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm. Extract will get a C language file, which is the code and hardware co-ordination Nios2_C
Platform: | Size: 5120 | Author: 于艳超 | Hits:

[Other] PWM_GEN

Description: 这是Altera PWM生成的一个实例。包含project文件，源代码，仿真文件。经过验证，实际可用。-This is an example of Altera PWM generated. Contains the project files, source code, simulation files. After verification, the actual available.
Platform: | Size: 250880 | Author: 洛空奇 | Hits:

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[VHDL-FPGA-Verilog] vcpwmcpldcar

[VHDL-FPGA-Verilog] Source

[VHDL-FPGA-Verilog] PWM_CT

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] SVPWM

[VHDL-FPGA-Verilog] FPGA_PWM

[SCM] Source

[SCM] pwm

[VHDL-FPGA-Verilog] pmw2ppm

[VHDL-FPGA-Verilog] pwm_gen

[VHDL-FPGA-Verilog] fpga-pwm

[Driver Develop] FPGA_SOPC_PWM

[Other] PWM_GEN

[VHDL-FPGA-Verilog] test4

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] pwm_timer

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] samlecode.vhdl

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] PWM

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